Description: This course is designed to provide a foundational understanding of modern microprocessor architecture and how they execute application programs. We will delve into the fundamental concepts and strategies involved in computer design, including designing instruction set architectures (ISAs) and optimizing processor micro-architecture to improve instruction-level parallelism (ILP) and memory-level parallelism (MLP). We will cover topics such as pipelining, branch prediction, super-scalar architecture, out-of-order execution, cache prefetching, and power optimizations, among others.
Instructors: Blaise-Pascal Tine ([email protected])
Office Hours: F 4:30-5:30 pm at EVI 499
Teaching Assistant: ****Turan Vural ([email protected])
Office Hours: TBD
Units: 4 credits