lecture5.pptx

JALR:

• Target address - sign extended + src1
• Link register rd

Conditional branches:

• Compare rs1 and rs2
• Target address = sign-extended 12-bit immediate + PC

LOAD:

• rd = MEM[base + offset]
• width = size of word
  • LB (load byte): 000
  • LH: (load half word): 001
  • LW (load word): 010
  • LBU (load b unsigned): 100
  • …

Problem:

Given a 32-bit RISC-V CPU. Memory segment starting at 0x10010000 (stored x2). Load (to x5) unsigned byte at 0x1001002A.

blu x5, 42(x2)

Loading into x2?

lui x2, 0x10010

imm[12:31]

STORE:

• MEM[base + offset] = src