lecture6.pptx

Privilege Levels

• User level
• Supervisor
• Hypervisor
• Machine

CPU starts at M

Software can use CSR status to lower privilege level

CPU uses exception handling to increase privilege level

RISC-V mret, sret, uret are system return instructions for switching back to previous after exception handling

Timers and Counters

• RD_CYCLE - total cycle
• RD_TIME - wall-clock
• RD_INSTRET - instruction timing

What about 32 bit systems? Read from bottom then top? What about syncing?

Just keep trying until they sync…

loop:
	csrrs x3, cycleh, x0
	csrrs x2, cycle, x0
	csrrs x4, cycleh, x0
	bne x3, x4, loop