Asynchronous Sequential Circuits

Stable states are marked with circles on a Karnaugh map (or flow table, with columns as input and rows as states).

Example with SR Latch:

$q/SR$ 00 01 11 10
0 (0) (0) X 1
1 (1) 0 X (1)

Fundamental Mode Restriction

Only one input can change at a time (setup/hold times for an FF).

Primitive flow table: One stable state each row

Example:

Control delay: Input $x$ coming infrequently synchronized with clock $c$. Output $z$ geos 1 one clock cycle after $x$ also synced with $c$.

$q/xc$ 00 01 11 10 00 (z) 01 (z) 11 (z) 10 (z)
1 (1) 2 0
2 1 (2) 3 0
3 (3) 4 0
4 5 (4) 0
5 (5) 6 0
6 1 (6) 1

Row 1: no clock, no input; when clock, go to state 2

Row 2: no clock, no input, is next clock tick, go to state 1; still clock, no input

Minimization: (1, 2) (3, 4, 5) (6)

$q/xc$ 00 01 11 10 00 (z) 01 (z) 11 (z) 10 (z)
a (a) (a) b - 0 0 0 -
b (b) c (b) (b) 0 - 0 0
c a (c) - - - 1 - -
$y_2y_1/xc$ 00 01 11 10 00 (z) 01 (z) 11 (z) 10 (z)
00 00 00 01 X 0 0 0 X
01 01 11 01 01 0 X 0 0
11 00 11 X X X 1 X X
10 X X X X X X X X

Races

Two or more state variables changing.

We can fix this by assigning adjacent states or adding spare states.

Designing a DFF