add x5, x1, x2
sub x20, x5, x4
However, the second instruction depends on x5, which has not been written back to the register file yet.
Instruction ordering should only be enforced externally.
Target address not yet available for branch
Resource sharing between instructions (prior still using resource that current instruction needs, such as IDIV)
Read after write
Error!
For the example above, wait two cycles (we can read and write in the same cycle due to forwarding)
WAW
Not an issue (may be issue with OOE)
WAR
Also not an issue
RAR
Also not an issue